Introduction:
Fixed-frequency peak current mode PWM (Pulse Width Modulation) offers significant advantages over traditional voltage mode control in DC-DC converters. These include excellent transient response, high output precision, and strong load capacity, making it widely adopted. As a key analog component, the slope compensation circuit and current sampling circuit form the foundation of current mode PWM control and play a crucial role in stabilizing the current loop within current mode control.
1. Circuit Structure:
Figure 1 presents the block diagram of a typical peak current mode PWM Boost DC-DC control system. When the voltage feedback signal from the voltage outer loop is sent through the error amplifier VE, it is compared with a triangular wave or trapezoidal sharp-angled composite wave whose peak represents the peak inductor current. This comparison generates a PWM pulse turn-off threshold expressed as follows:
In equation (1), the first term represents the slope compensation portion, ensuring current loop stability; the second term reflects the inductor current's magnitude, typically generated by the current sampling circuit; the third term serves as a fixed base level for the PWM comparator, providing an appropriate DC operating point.
Thus, the peak current mode control indirectly manages the PWM pulse width by controlling the peak inductor current rather than directly manipulating the voltage error signal.
However, the current mode structure suffers from inherent issues such as open-loop instability, subharmonic oscillation, non-ideal loop responses, and increased susceptibility to noise when the duty cycle exceeds 50%. To address these challenges, the current loop requires compensation, along with the voltage loop, to meet stability requirements. A practical solution involves using slope compensation techniques while improving current sampling accuracy to enhance loop stability.
In this study, the V/I conversion of the voltage on the oscillator charge and discharge capacitor achieves a stable slope with adjustable slope characteristics. Additionally, the power SENSEFET is utilized as the sampling device, allowing for independent V/I conversion without combining factors related to temperature and process. This approach ensures more precise sampling values while reducing losses.
2. Circuit Principle Analysis:
2.1 Slope Compensation:
Figure 2 demonstrates the method of superimposing slope compensation voltage onto the error signal VE. VE represents the error amplification signal of the voltage feedback loop. The solid-line waveform depicts undisturbed inductor current, while the dashed line shows the inductor current affected by ΔI0 disturbance. D indicates the duty ratio, and m1 and m2 represent the respective rise and freewheeling slopes obtained through sampling.
From Figures 2(a) and (b), it becomes evident that without slope compensation, the disturbance current in the next cycle would be:
After n cycles, the current error ΔIn caused by ΔI0 would be:
From equation (3), we see that when m2 < m1, i.e., D < 50%, the current error ΔIn gradually approaches zero, leading to system stability. Conversely, when m2 > m1, i.e., D > 50%, the current error ΔIn increases progressively, causing system instability.
Figure 2(c) illustrates the inductor current waveform after applying compensation voltage at D > 50%. For this waveform, the following applies:
To stabilize the loop, it is essential to make ΔI1 < ΔIo, satisfying:
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In summary, slope compensation plays a vital role in stabilizing the current loop, particularly when dealing with duty cycles exceeding 50%. By incorporating slope compensation techniques and optimizing current sampling, we can achieve better system performance and stability. This study highlights the importance of addressing inherent limitations in current mode control systems and offers practical solutions to enhance their overall efficiency and reliability.
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