Ultrasound has always been a crucial technology in the medical equipment field, known for its strong penetration and high detection sensitivity. However, its applications are no longer limited to healthcare; it is now widely used in industries such as aerospace and metallurgy. Today, ultrasonic flaw detectors use either analog or digital non-destructive testing technologies. With advancements in computer technology, microelectronics, and digital signal processing, traditional analog ultrasonic flaw detectors are gradually being replaced by more advanced digital ones.
The echo signal from an ultrasonic wave is a high-frequency signal, with a center frequency reaching up to 20 MHz. Typically, the frequency of signals from common ultrasonic probes ranges between 2.5 and 10 MHz. Digitizing such high-frequency signals places significant demands on the analog-to-digital (A/D) conversion circuit. According to the Shannon sampling theorem and the Nyquist criterion, to accurately reconstruct a signal without distortion, the sampling rate must be at least twice the highest frequency present. In practice, to ensure data accuracy, the number of samples per signal cycle should be increased—usually 7 to 10 times. Some systems require even higher sampling frequencies. Current A/D circuits face challenges in reliability, power consumption, speed, and precision, making them unsuitable for certain applications. The development of large-scale integrated circuits now offers high-speed, high-precision, reliable, and low-power solutions for ultrasound signal acquisition.
This paper presents a 100 MHz sampling-rate ultrasonic acquisition module, which compresses sampled data using an FPGA to buffer the information effectively. The design focuses on key technologies such as A/D conversion and data buffering, aiming to improve performance and efficiency.
**1. Principle of Digital Ultrasonic Flaw Detectors**
Figure 1 shows the block diagram of a digital ultrasonic flaw detector. It generally includes an ultrasonic transmitter, receiver, signal conditioning unit (amplification, filtering, etc.), A/D converter, data buffer, data processing unit, waveform display, and system control. This paper primarily discusses the implementation of high-speed data acquisition, focusing on the A/D and data buffer units.
**2. High-Speed, High-Precision Sampling Hardware Structure**
**2.1 Data Acquisition Module Block Diagram**
Figure 2 illustrates the hardware structure of the data acquisition module, consisting of a high-speed A/D converter, FPGA, clock circuit, reset circuit, and power supply. The A/D converter handles signal acquisition and conversion, while the FPGA manages control, compression, and buffering.
**2.2 Introduction to AD9446**
The AD9446 is a 16-bit ADC with a maximum sampling rate of 100 MSPS, featuring a built-in sample-and-hold amplifier and reference voltage source. It supports differential input, offering excellent rejection of common-mode and even signals. The AD9446 can operate in CMOS or LVDS mode, with output options including binary or two’s complement. For PCB design, careful attention must be paid to isolation of analog and digital grounds, equal-length differential lines, and accurate reference voltage.
**2.3 FPGA Implementation of Acquisition Control, Data Compression, and Buffering**
The FPGA, specifically the Xilinx Spartan3E series (XC3S500E), controls the acquisition process, performs data compression, and manages data buffering. This section details the design of acquisition timing, compression algorithms, and FIFO-based data storage.
**2.3.1 Data Acquisition Control**
The AD9446 relies entirely on clock signals for sampling and data output. The Digital Clock Manager (DCM) within the FPGA adjusts clock frequencies and phases, ensuring synchronization with the ADC.
**2.3.2 Data Compression**
To reduce data volume while preserving signal integrity, only the maximum sampled value is retained during each compression cycle. This approach ensures compatibility with network transmission protocols.
**2.3.3 Data Buffering**
An internal FIFO buffer within the FPGA stores compressed data, allowing efficient data transfer to the microprocessor via interrupts. The FIFO size is configurable based on available FPGA resources.
**3. Conclusion**
This paper presents a high-performance data acquisition module using AD9446 and FPGA. It enhances system reliability, simplifies hardware, and improves scalability. The high-speed A/D converter ensures accurate data acquisition, while FPGA preprocessing facilitates efficient data handling and post-processing.
The JUK universal Screw Terminal Block series has the typical features which are decisive for practical applications:
l The universal foot allows the terminal blocks to be easily snapped onto the NS35 or NS32 DIN Rail with G shape.
l Closed screw guide holes ensure screwdriver operation perfect.
l For terminal block with different wire cross-sectional areas, complete accessories are available, such as end plates, partition plates, etc.
l Potential distribution achieved by fixed bridges in the terminal center or insertion bridges in the clamping space.
l Same shape and pitch Grounding Terminal Blocks as the JUK universal series.
l Adopt ZB marker strip system,achieve unified identification.
Screw Terminal Block Types,Beige Screw Terminal Block,Good Quality Terminal Block,Screw Terminal Blocks
Wonke Electric CO.,Ltd. , https://www.wkdq-electric.com