Ultrasound has long been a crucial technology in the medical equipment field, known for its strong penetration and high sensitivity. However, its applications are no longer limited to healthcare; it is now widely used in aerospace, metallurgy, and other manufacturing industries. Today, ultrasonic flaw detectors employ either analog or digital non-destructive testing techniques. With the advancement of computer technology, microelectronics, and digital signal processing, traditional analog ultrasonic flaw detectors are gradually being replaced by more advanced digital models.
The echo signal from an ultrasonic wave is a high-frequency signal, with a center frequency reaching up to 20 MHz. In most cases, the frequency of the echo signal from a standard ultrasonic probe ranges between 2.5 and 10 MHz. Digitizing such a high-frequency signal places significant demands on the analog-to-digital (A/D) conversion circuit. According to the Shannon sampling theorem and Nyquist criterion, to accurately reconstruct the input signal without distortion, the sampling frequency must be at least twice the highest frequency of the signal. In practice, to ensure data accuracy, the number of samples per cycle is usually increased to 7–10 times. Some systems require even higher sampling frequencies. Existing A/D circuits have limitations in reliability, power consumption, speed, and precision, which make them unsuitable for certain real-world applications. The development of large-scale integrated circuits now allows for high-speed, high-precision, reliable, and low-power ultrasound signal acquisition solutions.
This paper presents a 100 MHz sampling rate ultrasonic acquisition module, where the collected data is compressed using an FPGA to manage data buffering efficiently.
**1. Principle of Digital Ultrasonic Flaw Detector**
Figure 1 shows the block diagram of the structure of a digital ultrasonic flaw detector. The system typically includes an ultrasonic transmitter, receiver, signal conditioning unit (such as amplification, filtering, and detection), A/D converter, data buffer, data processing unit, waveform display, and a control and I/O unit (including communication, keyboard, and alarm functions). This paper focuses on the key technologies involved in high-speed data acquisition, particularly the A/D conversion and data buffer units.
**2. High-Speed, High-Precision Sampling Hardware Structure**
**2.1 Block Diagram of the Data Acquisition Module**
Figure 2 illustrates the hardware block diagram of the data acquisition module, consisting of a high-speed A/D converter, FPGA, clock circuit, reset circuit, and power supply. The A/D converter handles signal acquisition and conversion, while the FPGA manages data control, compression, and buffering. The following sections describe the A/D converter and FPGA in detail.
**2.2 Introduction to AD9446**
The AD9446 is a 16-bit ADC with a maximum sampling rate of 100 MSPS, featuring an integrated sample-and-hold amplifier and reference voltage source. It supports differential inputs, offering excellent rejection of common-mode and even signals. The AD9446 can operate in CMOS or LVDS mode, with mode selection controlled via logic pins. Its digital output can be set to binary or two's complement. When designing the PCB, special attention should be given to separating analog and digital grounds, ensuring equal-length differential lines, and using a stable reference voltage.
**2.3 FPGA Implementation for Acquisition Control, Data Compression, and Buffering**
The FPGA, specifically the Xilinx Spartan3E series (XC3S500E), is responsible for managing data acquisition control, compression, and buffering. The following sections discuss the design of the control logic, data compression, and FIFO-based data buffering.
**2.3.1 Data Acquisition Control**
The AD9446 operates based on clock signals, with sampling initiated on the rising edge of the first clock pulse. The data becomes available after a delay. The FPGA uses a Digital Clock Manager (DCM) to generate and control the clock signal for the AD9446. The VHDL code for the clock output is provided below.
**2.3.2 Data Compression**
Data compression is essential for handling high-frequency RF signals. To maintain the integrity of the ultrasonic echo, only the maximum sampled value is retained during each compression cycle. The FPGA calculates the compression ratio, sends the data to a latch, and controls the timing for the next sampling. This process continues until the compression count reaches zero, ensuring efficient data storage.
**2.3.3 Data Buffering**
To address the issue of data rate mismatch, a FIFO buffer is implemented within the FPGA. The FIFO is 8K × 16 bits in size, and the compressed data is stored directly into it. The microprocessor reads the data through an interrupt mechanism. The VHDL code for the instantiated FIFO is also provided.
**3. Conclusion**
This paper presents a data acquisition module based on the AD9446, integrating data control, compression, and buffering. It simplifies the hardware, improves reliability, and facilitates future upgrades. The use of a high-speed, high-precision ADC ensures accurate data acquisition for digital ultrasonic flaw detection. Additionally, the FPGA preprocessing makes it easier for the microprocessor to access and process the data efficiently.
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