High-performance CMOS charge pump design - News - Global IC Trade Starts Here.

Full range MOS power IC

Probe current-voltage pin with 420x4450 resolution, head diameter 5.0mm; supports overcurrent detection and pin current and voltage monitoring

Inductance measurements and analysis

SMD aluminum electrolytic capacitors for enhanced performance

Abstract: This paper presents the design of a CMOS charge pump circuit for charge pump phase-locked loops (CPPLLs). The circuit employs three pairs of self-biased high-swing cascode current mirrors to mirror the pump current, enhancing the output resistance of the charge pump at low voltages while ensuring matching between the upper and lower charge pumps. To address the charge sharing issue inherent in single-ended charge pumps, a half-differential current switch structure with bandwidth amplitude voltage following is introduced, improving the overall performance of the charge pump. The design utilizes a 0.18μm standard CMOS process. Simulation results indicate that the pump current matching accuracy is 0.9% across the voltage range of 0.35 to 1.3 V, with the circuit operating at a frequency of 250 MHz.

Keywords: Charge pump; Phase-locked loop; Self-biased cascode current mirror; Voltage follower

CPPLLs offer numerous advantages, including high-speed operation, low power consumption, low jitter, and cost-effectiveness, making them widely applicable in frequency synthesis and clock recovery circuits. As a critical component of the CPPLL, the charge pump often encounters non-ideal effects such as switching delay, current mismatch, charge injection, and charge sharing during implementation. To minimize phase noise and spurious signals, achieve smoother output currents, reduce harmonic components in the output voltage, and minimize switching delays, this study proposes a high-output-impedance, high-charge-discharge-current-matching-ratio charge pump circuit based on a pseudo-differential structure.

1. Charge Pump Design Analysis: The primary function of the charge pump is to convert the output signal from the phase-frequency detector (PFD) into a continuously varying analog voltage signal to control the oscillation frequency of the voltage-controlled oscillator (VCO). When the PFD's up output signal is active, the charge pump's current source charges the loop filter, causing the VCO's voltage control terminal voltage to rise and adjust the oscillation frequency accordingly. Conversely, the down signal triggers the charge pump current sink to discharge the loop filter, reducing the VCO's voltage-controlled voltage. Ideally, when the VCO's oscillation frequency and phase match the reference signal, the charge pump's output should stabilize at a constant value. However, traditional charge pumps, as depicted in Figure 1, suffer from several non-ideal effects, including charge leakage, current mismatch, charge sharing, and pump switching delays. A well-designed charge pump should aim to mitigate these issues within design specifications.

[3][4]