High-performance CMOS charge pump design - News - Global IC Trade Starts Here.

MOS Power IC Full Range

Probe Current Voltage Pin 420×4450 Head Diameter 5.0 Overcurrent Current and Voltage Pin

Inductance

SMD Aluminum Electrolytic Capacitor

Abstract: A CMOS charge pump circuit for charge pump phase-locked loops (CPPLLs) has been designed. This circuit employs three pairs of self-biased high-swing cascode current mirrors to mirror the pump current, thereby increasing the output resistance of the charge pump at low voltages and achieving matching between the upper and lower charge pumps. To address the issue of charge sharing in single-ended charge pumps, a half-differential current switch structure with bandwidth amplitude voltage following was introduced to enhance the pump's performance. The design was fabricated using a 0.18 μm standard CMOS process. Simulation results indicate that the pump current matching accuracy is 0.9% within the voltage range of 0.35 to 1.3 V, and the circuit operates at a frequency of 250 MHz.

Key Words: charge pump; phase-locked loop; self-biased cascode current mirror; voltage follow

CPPLLs offer advantages such as high speed, low power consumption, low jitter, and low cost, making them widely applicable in frequency synthesis and clock recovery circuits. As a critical component of the CPPLL, the charge pump often encounters non-ideal effects like switching delay, charge and discharge current mismatch, charge injection, and charge sharing during implementation. For high-performance phase-locked loop designs, minimizing phase noise and spurious signals, ensuring smooth output current, reducing harmonic components in the output voltage, and decreasing switching delays are essential. Therefore, this paper proposes a high-output-impedance charge pump circuit with a high charge-discharge current matching ratio, employing a pseudo-differential structure.

1 Charge Pump Design Analysis The primary function of the charge pump is to convert the output signal from the phase frequency detector (PFD) into an analog continuously varying voltage signal to regulate the oscillation frequency of the voltage-controlled oscillator (VCO). When the up output signal from the PFD is active, the current source of the charge pump charges the loop filter, causing the voltage at the VCO’s control terminal to rise, which adjusts the VCO’s oscillation frequency accordingly. Conversely, the down signal triggers the charge pump current sink to discharge the loop filter, reducing the VCO’s control voltage. Ideally, when the VCO’s oscillation frequency and phase match the reference signal, the charge pump’s output should remain constant. However, traditional charge pumps, as illustrated in Figure 1, exhibit various non-ideal effects, including charge leakage, charge and discharge current mismatch, charge sharing, and pump switching delay. A well-designed charge pump must aim to minimize these issues within acceptable design limits.

[3][4]