In recent years, through-silicon vias (TSVs) have experienced rapid development. This technology offers significant advantages such as low power consumption, compact size, high performance, and high stacking density. As a result, it has gained widespread recognition within the industry and is seen as a key enabler for continuing Moore’s Law. In this article, we provide an overview of the TSV process flow and key technologies involved, including critical steps like etching, separation, metal filling, and copper exposure.
1. Overview
Three-dimensional integrated circuits (3D ICs) are considered promising solutions to overcome the limitations of Moore’s Law due to their low power consumption, small form factor, high performance, and high stacking density. To achieve 3D integration, several essential technologies must be employed, such as through-silicon vias (TSVs), wafer thinning, and wafer/chip bonding. Among these, TSV interconnects stand out because they reduce signal path lengths and enable smaller package sizes, making them a core component in 3D integration. TSV technology can be categorized into three main types: through-hole technology performed before the CMOS process, through-hole technology executed during the CMOS or back-end-of-line (BEOL) process, and back via technology applied after the CMOS process but before wafer thinning. The choice of which method to use depends on specific production requirements.
TSV technology has found applications in various products, including MEMS, mobile phones, CMOS image sensors (CIS), bio-applications, and memory devices. This indicates that there are already numerous research efforts and technological achievements in the field. However, due to relatively high costs, the widespread adoption of TSV technology combined with advanced packaging techniques for 3D integration remains limited. In this paper, we review the TSV manufacturing process, focusing on deep via reactive ion etching (DRIE), insulating liners, barrier and seed layers, via filling, and chemical mechanical polishing (CMP). We also discuss important processes such as copper exposure in detail.
2. TSV Structure and Manufacturing Process
2.1 TSV Structure
The TSV structure typically consists of a through-hole processed in a silicon wafer, with electroplated copper pillars, an insulating layer, and a barrier layer arranged from the inside out. The insulating layer serves to isolate the silicon wafer from the conductive material inside the via. Silicon dioxide is commonly used for this purpose. However, during the TSV fabrication process, copper atoms may diffuse through the insulating layer, leading to device degradation or failure. To prevent this, a barrier layer made of a more chemically stable metal is often placed between the copper and the insulating layer. Initially, tungsten was used for filling due to its low thermal expansion coefficient, but copper has since become the preferred material due to its superior conductivity.
2.2 TSV Manufacturing Process
The TSV manufacturing process involves the following steps:
(1) A photoresist is applied to define the etched area, followed by deep reactive ion etching (DRIE) to create a blind via on one side of the silicon wafer.
(2) An insulating layer, typically silicon dioxide, is deposited using chemical vapor deposition (CVD), followed by a titanium (Ti) barrier layer and a copper (Cu) seed layer deposited via physical vapor deposition (PVD).
(3) Electroplating is used to fill the via with copper.
(4) Excess copper on the surface is removed using chemical mechanical polishing (CMP).
(5) A redistribution layer (RDL) is formed on the side of the wafer containing the via.
(6) The RDL is bonded to a carrier wafer using a temporary adhesive.
(7) The other end of the copper column is exposed using CMP and back grinding.
(8) A under bump metallization (UBM) layer is fabricated on the backside of the wafer.
(9) Microbumps are then created on the backside.
(10) Finally, the wafer with microbumps is separated from the carrier, and the temporary adhesive is removed [1].
3. Key Technologies in TSV Production
3.1 TSV Etching
Deep silicon etching is a crucial step in TSV fabrication. The Bosch process is widely used, offering high etch rates (up to 5–10 μm/min) and good selectivity. However, this process can lead to rough sidewalls, which may cause issues in subsequent steps such as leakage and reliability problems. As TSV dimensions shrink, minimizing sidewall roughness becomes increasingly important.
3.2 TSV Insulation
An insulating layer is necessary to electrically isolate the silicon substrate from the filled metal. Common materials include silicon dioxide and silicon nitride, deposited via PECVD or SACVD. For sub-3 μm TSVs, atomic layer deposition (ALD) is preferred due to its better step coverage and lower thermal budget.
3.3 TSV Barrier Layer and Seed Layer
A barrier layer is deposited to prevent copper diffusion during annealing. Materials such as Ti, Ta, TaN, and TiN are commonly used. The seed layer, usually deposited via PVD, ensures uniform copper growth. Advanced methods like ALD and electroless plating are being explored to improve coverage and reduce costs.
3.4 TSV Filling
There are three primary methods for filling TSVs with copper: conformal plating, bottom-up sealing bump plating, and superconformal plating. Each method has its own advantages and challenges, particularly in terms of void formation and aspect ratio compatibility. Optimization of plating parameters, such as pulse current waveforms, is critical for achieving high-quality fills.
3.5 TSV Copper Exposure
Thermal mismatch between copper and silicon can lead to reliability issues such as cracking and delamination. Annealing and CMP are used to mitigate these effects. Proper pre-annealing and post-CMP steps help ensure long-term stability of the TSV structure.
4. Conclusion
This paper provides a comprehensive review of TSV manufacturing techniques in 3D integration, covering process development, copper filling methods, and the use of dielectric, barrier, and seed layers to address challenges like sidewall roughness and high aspect ratios. Wet processes help overcome copper seed discontinuities, while three main plating methods—conformal, bottom-up, and superconformal—offer different advantages depending on application needs. TSV gaps can cause electrical failures, and understanding their root causes is essential. With its benefits of compact size, high density, and cost-effectiveness, TSV technology holds great promise for future 3D integration solutions.
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