Abstract: This paper presents a high-speed, low-voltage, and low-power 32/33 dual-mode prescaler designed using TSMC 90nm 1P9M 1.2V CMOS technology, suitable for WLAN IEEE 802.11a communication standards. The circuit was simulated using Mentor Graphics Eldo, and the results show that it consumes only 0.8mW at 5.8GHz operation with a maximum operating frequency of 6.25GHz. The design focuses on optimizing performance for high-frequency applications while maintaining low power consumption.
Keywords: dual-mode prescaler, single-phase clock, high speed, low power consumption
0. Introduction
With the rapid advancement in mobile communication technologies, there is an increasing demand for RF circuits that operate at higher speeds while consuming less power. A phase-locked loop (PLL)-based frequency synthesizer plays a critical role in the front-end of a transceiver by providing a clean local oscillator signal for the mixer. Within the PLL, the voltage-controlled oscillator (VCO) and the prescaler are the two key components operating at the highest frequencies, making them the main limiting factors for the overall PLL performance. Enhancing the speed of the prescaler is therefore essential to pushing the upper frequency limit of the PLL system.
To meet the growing demands of high-frequency wireless communication systems, it is crucial to optimize both the prescaler and VCO for high speed and low power. Among various prescaler designs, the dual-mode prescaler has gained attention due to its flexibility in handling different frequency division ratios. It typically employs D flip-flops as the core building blocks. However, different D flip-flop architectures offer varying trade-offs between speed, power, and noise performance.
One common approach is the static SCL (Source-Coupled Logic) structure, which offers fast operation but requires a large number of MOSFETs, leading to higher power consumption. Another option is the dynamic TSPC (True Single-Phase Clock) structure, which reduces component count and improves speed with significantly lower power consumption, although it may suffer from worse noise immunity. Inductor-based designs, while offering good performance, are bulky and not ideal for integrated circuits. Choosing the right architecture depends on specific application requirements.
In this work, we implement a dual-mode prescaler using the dynamic TSPC structure, optimized for high speed, low voltage, and low power, based on TSMC 90nm 1P9M 1.2V CMOS technology, targeting the IEEE 802.11a standard.
1. Circuit Design
1.1 Overall Circuit Architecture
The basic structure of the dual-mode prescaler is illustrated in Figure 1. It consists of three main parts: a synchronous 2/3 divider, an asynchronous divide-by-2 chain, and a feedback section. The control signal MC determines the division ratio—32 when MC=1, and 33 when MC=0. The design aims to minimize power consumption by reducing the number of MOS transistors in the high-frequency synchronous divider unit.
Figure 1: Dual-mode pre-frequency divider structure
1.2 Synchronous Divider Design
The block diagram of the synchronous 2/3 divider is shown in Figure 2. As the most active part of the entire circuit, it directly affects the speed and power consumption of the prescaler. When MC is high, the circuit operates as a divide-by-2; when MC is low, it functions as a divide-by-3. This synchronous approach significantly reduces the number of MOS transistors in the high-frequency path, thus lowering power consumption.
Additionally, an AND gate is integrated into the D flip-flop, simplifying the overall design and eliminating parasitic effects that would otherwise degrade performance. This integration helps reduce speed loss and minimizes the conflict between speed and power consumption.
1.3 Power Consumption Optimization
The primary source of power consumption in the circuit comes from the synchronous 2/3 divider. Both the synchronous and asynchronous sections rely on D flip-flops, making the design of low-power, high-speed D flip-flops crucial for achieving optimal performance.
A commonly used Yuan-Svensson-type D flip-flop (falling-edge triggered) is shown in Figure 3. It uses dynamic CMOS technology with N-C2MOS, P-PrechargeCMOS, and P-C2MOS stages. While it improves upon traditional static designs, it still suffers from RC delays due to overlapping transistor layers. To address this, we modified the C2MOS circuit by replacing the N-C2MOS stage with a clocked pseudo PMOS inverter, reducing the number of transistors and load capacitance. Similarly, a clocked pseudo NMOS inverter replaces the P-C2MOS stage, forming a dynamic ratio latch as shown in Figure 4.
When the clock is low, the latch evaluates the input, and when it's high, it holds the output. This configuration lowers the RC delay, reducing both power consumption and propagation delay. However, during the evaluation mode, if the input D transitions from high to low, the output Q may invert, causing incorrect operation. To prevent this, a pseudo PMOS transistor is added at the input of the latch, as shown in Figure 5, ensuring that the output changes only once per cycle.
The final design is a negative-edge-triggered dynamic D flip-flop, as shown in Figure 5. Compared to the Yuan-Svensson structure, it uses three fewer transistors, improving driving capability and allowing for higher operating frequencies. Furthermore, the AND gate is integrated into the DFF, as depicted in Figure 6. Simulation results confirm that this design enhances both speed and power efficiency. In the synchronous 2/3 divider, DFF1 uses a D flip-flop without the AND gate, while DFF2 includes the integrated AND gate.
1.4 Asynchronous Divide-by-2 Divider
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