Abstract: This paper presents a high-speed, low-voltage, and low-power 32/33 dual-mode prescaler designed using TSMC 90nm 1P9M 1.2V CMOS technology, tailored for WLAN IEEE 802.11a communication standards. The circuit was simulated with Mentor Graphics Eldo, demonstrating a power consumption of only 0.8mW at 5.8GHz and an operational frequency up to 6.25GHz. The design leverages a dynamic TSPC (single-phase clock) structure to achieve both speed and efficiency, making it ideal for high-frequency wireless applications.
Keywords: dual-mode prescaler, single-phase clock, high speed, low power consumption, TSPC, CMOS
0 Preface
With the rapid development of mobile communication technologies, there is an increasing demand for high-speed and low-power radio frequency (RF) circuits. A key component in RF systems is the frequency synthesizer based on phase-locked loop (PLL) architecture, which plays a crucial role in generating a clean local oscillator signal for mixers. Within the PLL, the voltage-controlled oscillator (VCO) and the prescaler are the two components operating at the highest frequencies, often limiting the overall performance of the system. Enhancing the speed of the prescaler is therefore essential for pushing the upper frequency limits of the PLL. To meet the requirements of modern high-frequency communication systems, optimizing the design of both the prescaler and VCO for speed and power efficiency has become critical.
Dual-mode prescalers typically use D flip-flops as their core building blocks. In recent years, various high-speed D flip-flop structures have been proposed. One common type is the static SCL (source-coupled logic) structure, derived from ECL circuits, offering faster operation due to smaller signal swings. However, the typical SCL divider requires around 18 MOS transistors, leading to higher power consumption due to larger input capacitance. Another popular structure is the dynamic TSPC (True Single-Phase Clock) design, which uses a single-phase clock to reduce the number of components, resulting in lower power consumption and higher speed—ideal for pre-dividers. However, the dynamic single-ended nature of TSPC makes it more susceptible to noise compared to SCL. A third approach involves inductively coupled circuits, but these are bulky and rarely used in practice. Choosing the right structure depends on the specific application requirements.
In this work, we implement a dual-mode prescaler using the dynamic TSPC structure, designed for the WLAN IEEE 802.11a standard, utilizing TSMC 90nm 1P9M 1.2V CMOS technology. The design emphasizes high speed, low voltage, and low power consumption, making it suitable for advanced wireless communication systems.
1 Circuit Design
1.1 Overall Circuit Architecture
The basic structure of the dual-mode prescaler is shown in Figure 1. It consists of three main sections: a synchronous 2/3 divider, an asynchronous divide-by-2 chain, and a feedback mechanism. The control signal MC determines the division ratio: when MC is high, the circuit divides by 32; when MC is low, it divides by 33.
Figure 1: Dual-mode pre-frequency divider structure
The design reduces power consumption by minimizing the number of MOS transistors in the high-frequency synchronous section, while maintaining the necessary functionality for dual-mode operation.
1.2 Synchronous Divider Design
The block diagram of the synchronous 2/3 divider is illustrated in Figure 2. As the most active part of the entire circuit, it directly influences the speed and power consumption of the prescaler. When MC is high, the circuit operates as a divide-by-2; when MC is low, it becomes a divide-by-3. By using a synchronous 2/3 divider, the number of MOS transistors in the high-frequency portion is significantly reduced, thereby lowering the overall power consumption. Additionally, an integrated AND gate within the D flip-flop simplifies the design and minimizes parasitic effects, reducing speed loss and improving performance.
1.3 Power Consumption Optimization
As analyzed, the primary source of power consumption comes from the synchronous 2/3 frequency divider. Both the synchronous and asynchronous parts rely on D flip-flops, making their design critical for achieving high speed and low power.
Figure 3 shows a commonly used Yuan-Svensson-type D flip-flop (falling-edge triggered). This dynamic CMOS-based structure includes an N-C2MOS stage, a P-Precharge CMOS stage, and a P-C2MOS stage. While it improves performance over traditional static designs, the multiple overlapping stages introduce significant RC delays. To address this, we modified the C2MOS circuit by replacing the N-C2MOS with a clocked pseudo PMOS inverter, reducing the number of transistors and load capacitance. Similarly, a clocked pseudo NMOS inverter replaced the P-C2MOS, forming a dynamic ratio latch (Figure 4). When the clock is low, the latch evaluates; when high, it holds. This configuration reduces RC delay, lowers power consumption, and decreases transmission delay.
It should be noted that during evaluation mode (CLK low), if the input D changes from high to low, the output Q may invert, causing misoperation. To prevent this, a pseudo PMOS transistor is added at the input of the latch (Figure 5), ensuring that the input remains stable during evaluation. This results in a negative-edge-triggered dynamic D flip-flop that uses three fewer transistors than the original Yuan-Svensson design, enhancing clock drive strength and increasing the operating frequency. Additionally, the AND gate is integrated into the DFF, as shown in Figure 6. Simulations show that this integrated design improves speed and reduces power consumption. In the synchronous 2/3 divider, DFF1 uses a D flip-flop without an AND gate, while DFF2 incorporates one.
1.4 Asynchronous Divide-by-2 Divider
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