Introduction : Whether you are a logic designer, hardware engineer or system engineer, or even have all of these titles, as long as you use an FPGA in any high-speed and multi-protocol complex system, you will most likely need to work hard to solve the device. Configuration, power management, IP integration, signal integrity and other key design issues.
However, you don't have to face these challenges alone, because application engineers working in today's industry-leading FPGA companies face these issues every day, and they have come up with design guidelines that will make your design work easier. solution. Master the three golden rules of FPGA design to make your design easier.
1. The principle of balance of area and speed
The area here refers to the chip resources of the FPGA, including logic resources and I/O resources; the speed here refers to the highest frequency of FPGA operation (unlike DSP or ARM, the operating frequency of FPGA design is not fixed, and It is closely related to the delay of the design itself). In the actual design, using the smallest area to design the highest speed is the goal that every developer pursues, but "the fish and the bear's paw can't have both", and the wisdom of a developer is displayed between the trade-offs.
Speed ​​change area
The speed advantage can be exchanged for area savings. The smaller the area, the lower the cost of the product. The principle of speed change area is often used in some more complex algorithm designs. In these algorithm designs, pipeline design is often a must-have technique. In the pipeline design, these modules that are reused but used different times will consume a lot of FPGA resources. Transform the FPGA design technology, extract the smallest reuse unit from the reused algorithm module, and use this minimum high speed to replace the reused but different number of modules in the original design. Of course, in the process of transformation, some other resources will inevitably be added to realize this replacement process. But as long as the speed has an advantage, the added part of the logic can still achieve the purpose of reducing the area to increase the speed.
It can be seen that the key to the speed change area is the multiplexing of the high speed base unit.
2. Area change speed
In this method, the copying of the area can be exchanged for an increase in speed. The higher the speed of support, the higher product performance can be achieved. Some application areas that focus on product performance can use parallel processing technology to achieve area change speed.
Second, the hardware can achieve the principle
FPGA designs typically use HDL languages ​​such as Verilog HDL or VHDL. When using the HDL language to describe a hardware circuit function, it is important to ensure that the circuit described by the code is hardware achievable.
The syntax of the Verilog HDL language is very similar to the C language, but there is a fundamental difference between them. The C language is a high-level language-based language that can be run on the CPU after compilation. The Verilog HDL language description is itself a hardware structure, and is compiled into a hardware circuit. Therefore, some statements are not problematic in the C language environment, but in the HDL language environment, the results may be incorrect or not ideal. Such as:
For(i=0;i<16;i++)
DoSomething();
There is no problem running in C, but compiling in Verilog HDL environment will result in a serious waste of integrated resources.
Synchronous design principles
Synchronous and asynchronous circuits are two basic circuit configurations of FPGA design.
The biggest disadvantage of asynchronous circuits is that they produce glitch. The core circuit of the synchronous design is composed of various flip-flops. Any output of this type of circuit is generated by driving the flip-flop on the edge of a certain clock. Therefore, the synchronous design can well avoid the occurrence of burrs.
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