Abstract: K9K2GXXU0M is a large-capacity flash memory chip produced by Samsung. Its single-chip capacity can be as high as 256M. This article mainly introduces the features, pin functions, and operating instructions of the K9K2GXXU0M. It highlights the various operating states of the K9K2GXXU0M flash memory and gives their working sequences.
Keywords: flash memory; K9K2GXXU0M; large-capacity flash
Flash memory (FLASH MEMORY flash memory) is a type of memory that can be erased and erased, and the information is not lost after power-off. At the same time, the memory has the characteristics of non-volatile, low power consumption, and high flash writing speed, which can be widely used. In the field of external storage, such as personal computers and MP3, digital cameras. However, with the increasingly widespread use of flash memory, the requirements for the capacity of flash memory chips are also getting higher and higher. The original single chip capacities of 32M and 64M can no longer meet people's requirements. The emergence of K9K2GXXX0M just made up for this deficiency. The K9K2GXXX0M is the largest flash memory chip currently developed by Samsung and has a single chip capacity of up to 256M. It also provides 8M extra capacity. The flash memory chip is increased in capacity through a non-cell structure. The increase of chip capacity does not weaken the function of the K9K2GXXX0M. It can complete a 2112-byte programming operation within 400μs. It can also perform a 128k-byte erasure operation within 2ms, while the data in the data area can be 50ns. /byte speed read out.
The I/O port of the K9K2GXXU0M large-capacity flash memory chip can be used as either an address input terminal or an input/output terminal of data, and can also serve as an instruction input terminal. The on-chip write controller automatically controls all program and erase operations, including providing necessary repetitive pulses, internal acknowledgements, and data space.
1 K9K2GXXU0M performance parameters
The main features of K9K2GXXU0M are as follows:
Use 3.3V power supply;
The internal memory cell array of the chip is (256M+8.192M)bit×8bit, and the data register and buffer memory are (2k+64)bit×8bit;
An I/O port with instruction/address/data multiplexing;
In the power conversion process, its programming and erasing instructions can be suspended;
Due to the use of reliable CMOS moving gate technology, the chip can achieve a maximum of 100kB program/erase cycle. This technology can guarantee data storage for 10 years without loss.
Table 1 lists the programming and erasure characteristic parameters of the K9K2GXXU0M flash memory chip. The maximum time for tCBSY in the table depends on the interval between the completion of the internal programming and the data entry.
Table 1 Programming and Erase Characteristics of the K9K2GXXU0M Parameter Symbol Minimum Typical Maximum Units Programming Time tPROG 300 700μs Cache-Programmed Virtual Busy Time tCBSY 3 700μs Local Programming Loops in the Same Page Main Column NOP 4 Cycles Empty Column 4 Cycle Block Erase Time tBERS 2 3 ms
2 Pin description of K9K2GXXU0M
The K9K2GXXU0M has 48 pins and its pin arrangement is shown in Figure 1. The specific functions are as follows:
I/O0~I/O7: Data input/output port, I/O port is often used for input of instruction and address and data input/output, and data is input during reading. When the chip is not selected or cannot be output, the I/O port is in a high-impedance state.
CLE: Instruction latch, used to activate the instruction to the instruction register path, and latches the instruction on the rising edge of WE and CLE is high.
ALE: The address latch port is used to activate the address to the internal address register, and the address is latched on the rising edge of WE and ALE is high.
CE: Chip selection port is used to control the choice of equipment. When the device is busy, CE is ignored and the device is not able to return to the standby state.
RE: Read enable terminal, used to control the continuous output of data and send data to the I/O bus. Only at the falling edge of RE, the output data is valid. At the same time, it can also accumulate internal data addresses.
WE: The write enable control terminal is used to control the instruction writing of the I/O port. At the same time, the instruction, address, and data can be latched on the rising edge of the WE pulse via this port.
WP: write protection end, through the WP side can write protection in power conversion. When WP is low, its internal high generator resets.
Figure 3 programming operation timing diagram
R/B: Ready/Busy output, R/B output can show the operating status of the device. When R/B is low, a program, erase, or random read operation is in progress. After the operation is completed, R/B will automatically return high. Since this side is an open-drain output, it will not be in a high-impedance state even when the chip is not selected or the output is disabled.
PRE: Power on read operation, used to control the automatic read operation when power is on, PRE termination to VCC can realize the power on automatic read operation.
â— VCC: chip power supply.
â— VSS: Ground of the chip.
â— NC: Floating.
3 K9K2GXXU0M's bad block flash will produce bad blocks just like any other solid state memory. Bad blocks are blocks containing one or more invalid bits. Bad blocks in the K9K2GXXU0M do not affect the normal part of the work, because in the K9K2GXXU0M, the blocks are isolated. Bad blocks can be found by the address layout system, and the first block at 00h in K9K2GXXU0M must be normal. Bad blocks are also rewritable in most cases and cannot be restored once erased. Therefore, the system must be able to identify the bad block based on the bad block information and set up the bad block information table through the flow chart to prevent the bad block information from being erased.
In the use of flash memory, new bad blocks may be generated, causing some errors in normal operation. After an erase and program operation, if a read fails, a block swap should be performed. Block replacement is performed by a one-page buffer, and the rest of the block can be copied by finding an erasable empty block and reprogramming the current data object. In order to improve the efficiency of the use of storage space, when a read or acknowledgment error caused by a single byte error should be retracted by the ECC without any block replacement.
4 K9K2GXXU0M operating status
4.1 page read operation
The default state of K9K2GXXU0M is read state. The read operation is to write the 00h address to the instruction register through 4 address cycles as the start instruction. Once this instruction is latched, the read operation cannot be written on the next page.
When the address changes, a random read operation can store 2112 bytes of data in the selected page into the data register at 25μs. The system can determine whether the data transfer is completed by analyzing the output of the R/B pin. The data stored in the data register can be quickly read. For example, a page of data can be read out in 50 ns by continuous RE pulse.
Data can be randomly output from a page by writing a random data output instruction. The data address can be automatically found from the data address to be output by the random output instruction to the next address. Random data output operations can be used multiple times. Figure 2 shows the timing diagram for the read operation.
4.2 page programming
The K9K2GXXU0M is programmed on a page-by-page basis, but it supports multiple partial page programming in a single-page programming cycle, and the partial page has 2112 consecutive bytes. Writing a page program confirmation command (10h) starts the programming operation, but continuous data must be input before writing the command (10h).
Continuously Loading Data After writing a continuous data input instruction (80h), four cycles of address input and data loading will begin. However, unlike the programmed data, the word does not need to be loaded. The chip supports random input of data in the page, and can automatically change the address according to the random data input command (85h). Random data input can also be used multiple times. Figure 3 shows the timing diagram of its programming operation.
4.3 Cache Programming Cache programming is a form of page programming that can be performed by 2112-byte data registers and is valid in only one block. Because the K9K2GXXU0M has a page buffer, it can perform continuous data input when the data register is programmed into the memory cell. Cache programming can only begin after the completion of an unfinished programming cycle and the data register is passed from the cache. Through the R / B pin can determine whether the internal programming is completed. If the system only uses R/B to monitor the progress of the program, then the order of the last page of the target program must be scheduled by the current page programming instruction. If arranged by a cache programming instruction, the status bit must be determined before the last program is executed and the next operation starts. Figure 4 shows the cache programming operation timing diagram.
Figure 4 cache programming sequence diagram
4.4 Memory Bank Dubbing This function can quickly and efficiently rewrite the data in a page without requiring access to external memory. As the time spent on continuous access and reloading is shortened, the system's execution capability will increase. Especially when a part of the block is upgraded and the remaining part needs to be copied into a new block, its advantages are clearly shown. This operation is a continuous read command, but does not require continuous access to the destination address and copy the program. A read operation with the original page address instruction "35h" will transfer the entire 2112 bytes of data to the internal data buffer. When the chip returns to the ready state, a page copy data input instruction with a destination address loop is written. Errors in this operation are given by the "pass/fail" status. However, if the operation is performed for a long time, a bit operation error will be caused due to data loss, resulting in an external error "Check/correct" device check failure. For this reason, the operation should use two-bit error correction. Figure 5 shows the timing diagram for the memory copy operation.
Block erase
The erase operation of the K9K2GXXU0M is performed on a block basis. Block address loading starts with a block erase instruction and completes in two cycles. In fact, when the address lines A12 to A17 are left floating, only the address lines A18 to A28 are available. The erase confirmation command and the block address are loaded to start erasing. This operation must be performed in this order so that the contents of the memory are not affected by external noise and erase errors occur. FIG. 6 is a timing diagram of a block erase operation.
4.6 Reading Status
The status register in the K9K2GXXU0M can confirm whether the program and erase operations have completed successfully. After the instruction (70h) is written to the instruction register, the read cycle will output the contents of the status register to the I/O on the falling edge of CE or RE. The instruction register will remain in read state until a new instruction arrives, so if the status register is in a read state during a random read cycle, a read instruction should be given before the read cycle begins.
Figure 5 and Figure 6
5 Concluding remarks Since flash memory is non-volatile, rewritable, and does not lose data after a power failure, it is increasingly used. At the same time, as flash memory is widely used, its capacity requirements are also increasing. The emergence of the K9K2GXXU0M fills the gaps in large-capacity flash memory chips. K9K2GXXU0M not only has the advantage of large capacity, but also can complete a 2112byte programming operation in 400μs, and can complete the 128k byte erase operation in 2ms, so K9K2GXXU0M is a very good storage in the field of external storage. chip.
Keywords: flash memory; K9K2GXXU0M; large-capacity flash
Flash memory (FLASH MEMORY flash memory) is a type of memory that can be erased and erased, and the information is not lost after power-off. At the same time, the memory has the characteristics of non-volatile, low power consumption, and high flash writing speed, which can be widely used. In the field of external storage, such as personal computers and MP3, digital cameras. However, with the increasingly widespread use of flash memory, the requirements for the capacity of flash memory chips are also getting higher and higher. The original single chip capacities of 32M and 64M can no longer meet people's requirements. The emergence of K9K2GXXX0M just made up for this deficiency. The K9K2GXXX0M is the largest flash memory chip currently developed by Samsung and has a single chip capacity of up to 256M. It also provides 8M extra capacity. The flash memory chip is increased in capacity through a non-cell structure. The increase of chip capacity does not weaken the function of the K9K2GXXX0M. It can complete a 2112-byte programming operation within 400μs. It can also perform a 128k-byte erasure operation within 2ms, while the data in the data area can be 50ns. /byte speed read out.
The I/O port of the K9K2GXXU0M large-capacity flash memory chip can be used as either an address input terminal or an input/output terminal of data, and can also serve as an instruction input terminal. The on-chip write controller automatically controls all program and erase operations, including providing necessary repetitive pulses, internal acknowledgements, and data space.
1 K9K2GXXU0M performance parameters
The main features of K9K2GXXU0M are as follows:
Use 3.3V power supply;
The internal memory cell array of the chip is (256M+8.192M)bit×8bit, and the data register and buffer memory are (2k+64)bit×8bit;
An I/O port with instruction/address/data multiplexing;
In the power conversion process, its programming and erasing instructions can be suspended;
Due to the use of reliable CMOS moving gate technology, the chip can achieve a maximum of 100kB program/erase cycle. This technology can guarantee data storage for 10 years without loss.
Table 1 lists the programming and erasure characteristic parameters of the K9K2GXXU0M flash memory chip. The maximum time for tCBSY in the table depends on the interval between the completion of the internal programming and the data entry.
Table 1 Programming and Erase Characteristics of the K9K2GXXU0M Parameter Symbol Minimum Typical Maximum Units Programming Time tPROG 300 700μs Cache-Programmed Virtual Busy Time tCBSY 3 700μs Local Programming Loops in the Same Page Main Column NOP 4 Cycles Empty Column 4 Cycle Block Erase Time tBERS 2 3 ms
2 Pin description of K9K2GXXU0M
The K9K2GXXU0M has 48 pins and its pin arrangement is shown in Figure 1. The specific functions are as follows:
I/O0~I/O7: Data input/output port, I/O port is often used for input of instruction and address and data input/output, and data is input during reading. When the chip is not selected or cannot be output, the I/O port is in a high-impedance state.
CLE: Instruction latch, used to activate the instruction to the instruction register path, and latches the instruction on the rising edge of WE and CLE is high.
ALE: The address latch port is used to activate the address to the internal address register, and the address is latched on the rising edge of WE and ALE is high.
CE: Chip selection port is used to control the choice of equipment. When the device is busy, CE is ignored and the device is not able to return to the standby state.
RE: Read enable terminal, used to control the continuous output of data and send data to the I/O bus. Only at the falling edge of RE, the output data is valid. At the same time, it can also accumulate internal data addresses.
WE: The write enable control terminal is used to control the instruction writing of the I/O port. At the same time, the instruction, address, and data can be latched on the rising edge of the WE pulse via this port.
WP: write protection end, through the WP side can write protection in power conversion. When WP is low, its internal high generator resets.
Figure 3 programming operation timing diagram
R/B: Ready/Busy output, R/B output can show the operating status of the device. When R/B is low, a program, erase, or random read operation is in progress. After the operation is completed, R/B will automatically return high. Since this side is an open-drain output, it will not be in a high-impedance state even when the chip is not selected or the output is disabled.
PRE: Power on read operation, used to control the automatic read operation when power is on, PRE termination to VCC can realize the power on automatic read operation.
â— VCC: chip power supply.
â— VSS: Ground of the chip.
â— NC: Floating.
3 K9K2GXXU0M's bad block flash will produce bad blocks just like any other solid state memory. Bad blocks are blocks containing one or more invalid bits. Bad blocks in the K9K2GXXU0M do not affect the normal part of the work, because in the K9K2GXXU0M, the blocks are isolated. Bad blocks can be found by the address layout system, and the first block at 00h in K9K2GXXU0M must be normal. Bad blocks are also rewritable in most cases and cannot be restored once erased. Therefore, the system must be able to identify the bad block based on the bad block information and set up the bad block information table through the flow chart to prevent the bad block information from being erased.
In the use of flash memory, new bad blocks may be generated, causing some errors in normal operation. After an erase and program operation, if a read fails, a block swap should be performed. Block replacement is performed by a one-page buffer, and the rest of the block can be copied by finding an erasable empty block and reprogramming the current data object. In order to improve the efficiency of the use of storage space, when a read or acknowledgment error caused by a single byte error should be retracted by the ECC without any block replacement.
4 K9K2GXXU0M operating status
4.1 page read operation
The default state of K9K2GXXU0M is read state. The read operation is to write the 00h address to the instruction register through 4 address cycles as the start instruction. Once this instruction is latched, the read operation cannot be written on the next page.
When the address changes, a random read operation can store 2112 bytes of data in the selected page into the data register at 25μs. The system can determine whether the data transfer is completed by analyzing the output of the R/B pin. The data stored in the data register can be quickly read. For example, a page of data can be read out in 50 ns by continuous RE pulse.
Data can be randomly output from a page by writing a random data output instruction. The data address can be automatically found from the data address to be output by the random output instruction to the next address. Random data output operations can be used multiple times. Figure 2 shows the timing diagram for the read operation.
4.2 page programming
The K9K2GXXU0M is programmed on a page-by-page basis, but it supports multiple partial page programming in a single-page programming cycle, and the partial page has 2112 consecutive bytes. Writing a page program confirmation command (10h) starts the programming operation, but continuous data must be input before writing the command (10h).
Continuously Loading Data After writing a continuous data input instruction (80h), four cycles of address input and data loading will begin. However, unlike the programmed data, the word does not need to be loaded. The chip supports random input of data in the page, and can automatically change the address according to the random data input command (85h). Random data input can also be used multiple times. Figure 3 shows the timing diagram of its programming operation.
4.3 Cache Programming Cache programming is a form of page programming that can be performed by 2112-byte data registers and is valid in only one block. Because the K9K2GXXU0M has a page buffer, it can perform continuous data input when the data register is programmed into the memory cell. Cache programming can only begin after the completion of an unfinished programming cycle and the data register is passed from the cache. Through the R / B pin can determine whether the internal programming is completed. If the system only uses R/B to monitor the progress of the program, then the order of the last page of the target program must be scheduled by the current page programming instruction. If arranged by a cache programming instruction, the status bit must be determined before the last program is executed and the next operation starts. Figure 4 shows the cache programming operation timing diagram.
Figure 4 cache programming sequence diagram
4.4 Memory Bank Dubbing This function can quickly and efficiently rewrite the data in a page without requiring access to external memory. As the time spent on continuous access and reloading is shortened, the system's execution capability will increase. Especially when a part of the block is upgraded and the remaining part needs to be copied into a new block, its advantages are clearly shown. This operation is a continuous read command, but does not require continuous access to the destination address and copy the program. A read operation with the original page address instruction "35h" will transfer the entire 2112 bytes of data to the internal data buffer. When the chip returns to the ready state, a page copy data input instruction with a destination address loop is written. Errors in this operation are given by the "pass/fail" status. However, if the operation is performed for a long time, a bit operation error will be caused due to data loss, resulting in an external error "Check/correct" device check failure. For this reason, the operation should use two-bit error correction. Figure 5 shows the timing diagram for the memory copy operation.
Block erase
The erase operation of the K9K2GXXU0M is performed on a block basis. Block address loading starts with a block erase instruction and completes in two cycles. In fact, when the address lines A12 to A17 are left floating, only the address lines A18 to A28 are available. The erase confirmation command and the block address are loaded to start erasing. This operation must be performed in this order so that the contents of the memory are not affected by external noise and erase errors occur. FIG. 6 is a timing diagram of a block erase operation.
4.6 Reading Status
The status register in the K9K2GXXU0M can confirm whether the program and erase operations have completed successfully. After the instruction (70h) is written to the instruction register, the read cycle will output the contents of the status register to the I/O on the falling edge of CE or RE. The instruction register will remain in read state until a new instruction arrives, so if the status register is in a read state during a random read cycle, a read instruction should be given before the read cycle begins.
Figure 5 and Figure 6
5 Concluding remarks Since flash memory is non-volatile, rewritable, and does not lose data after a power failure, it is increasingly used. At the same time, as flash memory is widely used, its capacity requirements are also increasing. The emergence of the K9K2GXXU0M fills the gaps in large-capacity flash memory chips. K9K2GXXU0M not only has the advantage of large capacity, but also can complete a 2112byte programming operation in 400μs, and can complete the 128k byte erase operation in 2ms, so K9K2GXXU0M is a very good storage in the field of external storage. chip.